Method and circuit for controlling a plasma panel

ABSTRACT

A method for controlling cells of a plasma screen of array type, formed of cells arranged at the intersections of lines and columns, including the step of sequentially applying to each line an activation potential and, during the activation of a line, applying an activation potential to selected columns, in which, while a line is activated, the selected columns are non-simultaneously activated.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to plasma screens and more specifically tothe control of cells of a plasma screen.

2. Discussion of the Related Art

A plasma screen is an array type screen formed of cells arranged at theintersections of lines and columns. A cell includes a cavity filled witha rare gas, and at least two control electrodes. To create a light pointon the screen, by using a given cell, the cell is selected by applying apotential difference between its control electrodes, after which thecell gas is ionized, generally by means of a third control electrode.This ionization goes along with an emission of ultraviolet rays. Thecreation of the light point is obtained by excitation of a red, green orblue luminescent material by the emitted rays.

FIG. 1 shows a conventional structure of a plasma screen formed of cells4. Each cell 4 has two control electrodes respectively connected to aline 6 and to a column 8.

The selection of the cells, to create images, is performed,conventionally, by logic circuits generating control signals. The logicstates of these signals determine the cells that are controlled togenerate a light point and those that are controlled not to generateone. The ionization of a gas of a cell requires that potentials on theorder of some hundred volts be applied between the two controlelectrodes for a predetermined duration, on the order of 2 microseconds.Each cell has an equivalent capacitance on the order of several tens ofpicofarads.

FIG. 2 shows a plasma screen, the cells 4 of which are represented by anequivalent capacitor. A line control circuit 10 includes, for each line6, a line control block 14, an output of which is connected to line 6. Acolumn control circuit 12 includes, for each column 8, a column controlblock 18, an output 20 of which is connected to column 8. Circuits 10and 12 are generally integrated on a same semiconductor chip.

Conventionally, the cells of a plasma screen are activated line by line.The non-activated lines are set to a quiescent voltage VDD1 (forexample, 150 V). The activated line is brought to an activation voltageGND (0 V). To light chosen points of the activated line, thecorresponding columns are brought to a voltage VDD2 (80 V). The columnscorresponding to the other points of the activated line are brought tovoltage GND (0 V). Thus, the lit cells of the activated line see acolumn-line voltage equal to VDD2−GND (80 V) and the unlit cells of theactivated line see a column-line voltage equal to GND−GND (0 V). For allnon-activated lines, the line voltage is VDD1 (150 V) and the columnvoltage is 0 or 80 V. In both cases, the cells of the non-activatedlines are reverse biased.

Each line control block 14 includes a pair of complementary powertransistors 22 and 24. Transistor 24 receives voltage VDD1 on itssource. Its drain is connected to a line 6 and its gate receives a linedeactivation control signal LSN. The source of transistor 22 isconnected to voltage GND. Its drain is connected to line 6 and its gatereceives a control signal LS complementary to signal LSN. Signals LS andLSN are generated, for example, by a microprocessor, not shown.

Each column control block 18 includes an output stage 26 including acouple of power transistors (not shown) enabling bringing output 20 tovoltages VDD2 or GND according to a logic column selection signal LCSprovided to stage 26. Each control block 18 also includes a memoryelement 28 connected, for example, to a microprocessor, not shown, forreceiving and storing the value of logic signal LCS intended for outputstage 26. Each control block 18 further includes a logic switch 30controlled by an enable signal VAL, connected between memory element 28and output stage 26. Logic switch 30 is provided to provide an inactivesignal to output stage 26 as long as enable signal VAL is inactive, forexample at a low logic level. Switch 30 is also provided for, whensignal VAL is active, providing output stage 26 with signal LCS storedin memory element 28. Signal VAL is conventionally activated for apredetermined duration after each activation of a screen line.

FIG. 3 is a timing diagram illustrating voltage V6 of a line 6, enablesignal VAL, voltage V8 of a column 8, and current I22 in transistor 22of line control circuit 14. At a time t0, the line is selected andvoltage V6 switches from voltage VDD1 to voltage GND. Voltage V8 then isat GND. At a time t1, signal VAL is activated and column 8 is connectedto potential VDD2, for a point to be lit. The selected cell chargesbetween time t1 and a time t2 and voltage V8 switches from GND to VDD2.During this charge, transistor 22 conducts a first current peak P1. Forphysical reasons associated with the cell structure, a short time afterthis first current peak, a second current peak P2, more intense than thefirst one, occurs between times t3 and t4. As an example, time t1 mayoccur from 10 to 20 ns after time t0, time t2 may occur from 50 to 100ns after time t1, and times t3 and t4 may occur from 150 to 200 ns aftertimes t1 and t2, respectively. The charge of a cell can correspond tocurrent peaks P1 and P2 respectively of 0.1 and 0.3 mA. A controlcircuit is conventionally used to control more than 3000 columns. Thus,if all the columns 8 of a selected line must be lit, the second currentpeak crossing transistor 22 can reach 1 A. Transistors 22 must have alarge size to be able to conduct such a current.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a control circuit ofthe cells of a plasma screen, which is of reduced size and low cost.

To achieve this object, the present invention provides delaying theselection of the different columns so that the charge of the equivalentcapacitors of the cells in a same screen line is not simultaneous.

More specifically, the present invention provides a method forcontrolling cells of a plasma screen of array type, formed of cellsarranged at the intersections of lines and columns, including the stepof sequentially applying to each line an activation potential and,during the activation of a line, applying an activation potential toselected columns, in which, while a line is activated, the selectedcolumns are non-simultaneously activated.

According to an embodiment of the present invention, the activation ofthe selected columns is controlled by a single signal activating severalcontrol blocks, each of which controls with a specific delay theapplication of the activation potential to the column.

The present invention also aims at a circuit for controlling the cellsof a plasma screen of array type, formed of cells arranged at theintersections of lines and columns, including line control blocks forsequentially applying, to each line, an activation potential, andincluding column control blocks for, as each line is activated, applyingan activation potential to selected columns, each column control blockincluding a means with a predetermined delay for delaying theapplication of the activation potential to the selected columns.

According to an embodiment of the present invention, the predetermineddelay means of each column control block is connected to be activated bya same enable signal.

According to an embodiment of the present invention, each predetermineddelay means delays the application of the activation potential to aselected column with a predetermined delay from its activation.

According to an embodiment of the present invention, each column controlblock includes:

-   -   an output stage coupled to the column activated by the control        block, and receiving an input signal,    -   a memory element for receiving and storing a column selection        signal, and    -   a predetermined delay means including a NAND gate having a first        input connected at the output of the memory element, a second        input which receives said enable signal and an output connected        to the input of the output stage via an inverter including a        P-type MOS transistor, the dimensions of which are such that        said inverter switches at a predetermined speed.

According to an embodiment of the present invention, the column controlblocks form several groups, the column control blocks of a same groupeach activating a column with a same predetermined delay and each columncontrol block including:

-   -   an output stage coupled to the column activated by the control        block, and receiving an input signal,    -   a memory element for receiving and storing a column selection        signal, and    -   a predetermined delay means including a NAND gate having a first        input connected at the output of the memory element, a second        input which receives said enable signal and an output connected        to the input of the output stage via an inverter supplied        between a ground and a supply node, the supply nodes of the        column control blocks of a same group being interconnected and        separated from the supply nodes of the other column control        blocks by a resistor, the supply nodes of a first group of        column control blocks being connected to a supply voltage.

The foregoing and other objects, features and advantages of the presentinvention will be discussed in detail in the following non-limitingdescription of specific embodiments, in conjunction with theaccompanying drawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1, previously described, schematically shows a conventional plasmascreen structure;

FIG. 2, previously described, schematically shows a plasma screenconnected to a conventional control circuit;

FIG. 3, previously described, illustrates the charge of a cell of a lineof the screen of FIG. 2;

FIG. 4 schematically shows column control blocks according to thepresent invention;

FIG. 5 illustrates the charge of cells of a line of a plasma screencontrolled by the control circuit according to the present invention;

FIG. 6 schematically shows an embodiment of a logic switch of a columncontrol block according to the present invention; and

FIG. 7 schematically shows another embodiment of the logic switch of acolumn control block according to the present invention.

DETAILED DESCRIPTION

In the drawings, only those elements necessary to the understanding ofthe present invention have been shown. The same references represent thesame elements in the difference drawings.

FIG. 4 schematically shows a circuit 12′ for controlling the columns ofa plasma screen (not shown) according to the present invention. Circuit12′ includes, for each column 8 of the plasma screen, a column controlblock 18′, an output 20 of which is connected to column 8. Each controlblock 18′ includes an output stage 26 controlled by a logic columnactivation signal LCS, and a memory element 28 connected to receive andstore the value of the logic signal to be provided to stage 26. Eachcontrol block 18′ further includes a logic switch 30′ controlled by anenable signal VAL and connected between memory element 28 and outputstage 26. According to the present invention, the logic switch 30′ ofeach control block 18′ is provided for, when signal VAL is activated,providing the signal LCS stored in memory element 28 to output stage 26with a predetermined delay. The logic switches 30′ of the differentblocks 18′ may each introduce a different delay with respect to signalVAL, or they may be distributed into several groups of switchesintroducing the same delay. As the number of blocks 18′ introducing adifferent delay is increased, the number of cells is reduced, andtherefore the number of equivalent capacitors of the cells which need tobe simultaneously charged is reduced, and therefore the maximum currentconducted by transistor 22 is reduced.

FIG. 5 shows various voltages and currents appearing upon operation ofthe circuit of FIG. 4. V8a, V8b, V8c represent the voltages of threecolumns connected to three blocks 18′ according to the presentinvention, the logic switches of which respectively introduce delays Da,Db, Dc. At a time t0, a line 6 is selected and its voltage V6 switchesfrom potential VDD1 to potential GND. Voltages V8a, V8b, V8c then are atvoltage GND. Signal VAL is activated at a time t1. The logic switches30′ of the three blocks 18′ respectively generate activation signalsLCSa, LCSb, LCSc at times t1a, t1b, t1c delayed by Da, Db, Dc withrespect to time t1. Columns 8 a, 8 b, and 8 c are connected to potentialVDD2 substantially at times t1a, t1b, and t1c. The capacitors of thecells connected to columns 8 a, 8 b, and 8 c respectively charge betweentimes t1a and t2a, t1b and t2b, t1c and t2c. Transistor 22 conductsfirst current peaks P1 a, P1 b, P1 c on the order of 0.1 mA, each duringthe charge of each of the three capacitors. As seen previously, eachcharge is followed by a second current peak. Transistor 22 conductsthree second current peaks P2 a, P2 b, P2 c on the order of 0.3 mA, eachbetween times t3a and t4a, t3b and t4b, t3c and t4c. When all thecolumns 8 of a line must be lit by a by a column control circuitaccording to the present invention, the maximum current conducted bytransistor 22 is only equal to the sum of the current peaks generated byblocks 18′ introducing the same delay. If, for example, blocks 18′ aredistributed in three groups a, b, c respectively introducing a delay Da,Db, Dc, the present invention reduces by a factor of three the maximumcurrent in transistor 22.

It should be noted that in FIG. 5, the illustrated charge durations,that is, the width of the current peaks, and delays Da, Db, Dc, are suchthat the current peaks corresponding to the different delays aredistinct. In practice however, the charge durations and the delays maybe such that the different peaks overlap.

FIG. 6 schematically shows an embodiment of a logic switch 30′. Switch30′ includes a conventional NAND gate 34. The two input terminals ofgate 34 are the two input terminals of logic switch 30′. The output ofgate 34 is connected to output S of switch 30′ via an inverter 36.Inverter 36 includes an N-type MOS transistor connected between theground and output S and a P-type MOS transistor connected between outputS and a supply line VDD, for example 3 or 5 V. According to the presentinvention, the width-to-length ratio (W/L) specific to the P-type MOStransistor of inverter 36 is used to obtain a specific delay. The W/Lratio of the P-type transistor especially determines the current thatcan be conducted by this transistor, and thereby, the speed at whichswitch 30′ can bring a load (stage 26) connected to its output S to avoltage corresponding to a high logic state. Thus, the W/L ratio of theP-type MOS transistor of inverter 36 enables adjusting the delayintroduced by logic switch 30′.

FIG. 7 shows logic switches 30″ of a control circuit according toanother embodiment of the present invention. Each logic switch 30″includes a NAND gate 34, the inputs of which form the inputs of thelogic switch, and the output of which is connected to output S of logicswitch 30″ via an inverter 38. Each inverter 38 is supplied between asupply node A and the ground. According to the present invention, thelogic switches 30″ are distributed into n groups G1, G2, . . . Gn (wheren is an integer), introducing different delays. FIG. 7 shows groups oftwo switches 30″. Nodes A of switches 30″ belonging to a same group areinterconnected. Nodes A of the switches of group G1 are connected to asupply voltage VDD. Nodes A of the switches of group G2 are connected tonodes A of the switches of group G1 via a resistor 40. Similarly, nodesA of the switches of a group Gi (where i ranges between 2 and n) areconnected to nodes A of the switches of group Gi-1 via a resistor 40.

In this embodiment, inverters 38 of switches 30″ of a same group havethe same supply voltage and the inverters of two different groups havedifferent supply voltages. The speed at which each inverter can bring aload (stage 26) connected to its output S to a voltage corresponding toa high logic state depends on the supply voltage of this inverter. Thus,the delays introduced by switches 30″ of groups G1, G2, . . . Gn dependon the supply voltage of the respective inverters 38 of these switches.The supply voltage of inverters 38 depends on the voltage drops inresistors 40 and these voltage drops depend on the number of inverters38 with a state that switches. When the number of activated cells islarge, which, in prior art, would cause high current peaks in transistor22, the number of inverters 38 having a state that switches is large andthe voltage drops in resistors 40 are significant. As a result, thedelays introduced by switches 30″ of groups G1, G2, . . . Gn are long,which reduces the current peaks in transistor 22. When the number ofactivated cells is small, the number of inverters 38 having a state thatswitches is small and the voltage drops in resistors 40 are small. Thedelays introduced by switches 30″ of groups G1, G2, . . . Gn are thenshort and the line selection time is thus short. Such a control circuitthus operates at an optimal speed while having transistors 22 of reducedsize.

Of course, the present invention is likely to have various alterations,modifications, and improvements which will readily occur to thoseskilled in the art. In particular, embodiments of the present inventionin which the column activation signal is delayed from a single enablesignal VAL have been described, but those skilled in the art will easilyadapt the present invention to an embodiment in which several delayedenable signals VAL generated based on an initial signal VAL are used.

The present invention has been described in relation with logic switches(30′, 30″) provided for receiving and providing logic signals that areactive at a high state, but those skilled in the art will easily adaptthe present invention to logic switches provided for receiving andproviding logic signals that are active at a low state.

Further, the present invention has been described in relation with alogic switch (30′, 30″), the output of which is provided by an inverter(36, 38) provided for introducing a predetermined delay, but thoseskilled in the art will easily adapt the present invention to a logicswitch also including other elements (such as a logic NAND gate)provided for introducing a predetermined delay.

Such alterations, modifications, and improvements are intended to bepart of this disclosure, and are intended to be within the spirit andthe scope of the present invention. Accordingly, the foregoingdescription is by way of example only and is not intended to belimiting. The present invention is limited only as defined in thefollowing claims and the equivalents thereto.

1. A circuit for controlling an array of cells of a plasma screen, eachcell of the array of cells being disposed at a correspondingintersection of one of a plurality of lines and one of a plurality ofcolumns, comprising: a plurality of line control blocks, each linecontrol block configured to apply a line activation signal to acorresponding one of the plurality of lines; and a plurality of columncontrol blocks, each column control block configured to apply a columnactivation signal to a corresponding one of the plurality of columns,and each column control block comprising a delay device adapted tocontrol application of the activation signal to the column correspondingto the control block, a first of the plurality of column control blocksconfigured to provide a first delay in applying the activation signal tothe column of the plasma screen corresponding to the first control blockand a second of the plurality of column control blocks configured toprovide a second delay in applying the activation signal to the columnof the plasma screen corresponding to the second control block, thefirst delay being different than the second delay.
 2. The circuit ofclaim 1, wherein each of the delay devices is configured and arrangedsuch that a single enable signal activates each of the delay devices. 3.The circuit of claim 1, wherein at least one of the plurality of columncontrol blocks further comprises an output stage connected between adelay device and a corresponding column, to apply the column activationsignal to the corresponding column.
 4. The circuit of claim 1, whereinat least one of the plurality of column blocks control includes: a NANDgate having a first input for receiving a logic signal to controlapplication of the column activation signal to a corresponding one ofthe plurality of columns, a second input for receiving an enable signal;and a delay element to control the speed at which the activation signalis applied to the corresponding one of the plurality of columns, thedelay element having an input connected to an output of the NAND gate,and an output connected to the corresponding one of the plurality ofcolumns.
 5. The circuit of claim 4, wherein the delay element is aninverter.
 6. The circuit of claim 5, wherein the inverter includes anN-type MOS transistor connected between ground and an inverter output,and a P-type MOS transistor connected between a voltage supply line andthe inverter output.
 7. The circuit of claim 6, further comprising anoutput stage, connected between the inverter output and the column, toprovide the activation signal to the column.
 8. The circuit of claim 6,further comprising a memory element connected to the first input of theNAND gate to provide the logic signal.
 9. The circuit of claim 1,wherein the plurality of column control blocks form a plurality ofgroups, each of the column control blocks comprising one of theplurality of groups adapted to apply the column activation signal to acorresponding one of the plurality of columns at the same time as theothers comprising the one of the plurality of groups, and a first of theplurality of groups adapted to apply the column activation signal at afirst time and a second of the plurality of groups adapted to apply thecolumn activation signal at a second time.
 10. The circuit of claim 9,wherein each delay device is connected to ground and is connected to acorresponding voltage supply node, the delay elements comprising one ofthe plurality of groups being connected to one of the voltage supplynodes, each of the plurality of supply nodes being connected to anotherof the plurality of supply nodes by a corresponding resistor.
 11. Amethod of controlling an array of cells of a plasma screen, each cell ofthe array of cells being disposed at a corresponding intersection of oneof a plurality of lines and one of a plurality of columns, comprising:activating at least one of the plurality of lines; initiatingapplication of a first column activation signal to a first of theplurality of columns of the plasma screen, at a first time; andinitiating application of a second column activation signal to a secondof the plurality of columns of the plasma screen, at a second time, thesecond time being distinct from the first time, and both the first timeand the second time occurring during the activating step.
 12. The methodof claim 11, wherein the step of initiating application of a firstcolumn activation signal to a first of the plurality of columns includesswitching a first transistor connected between a first voltage and afirst output connected to a first of the plurality of columns, and thestep of initiating application of a second column activation signal to asecond of the plurality of columns includes switching a transistorconnected between a second voltage and a second output connected to asecond of the plurality of columns, the second voltage being differentthan the first voltage.
 13. The method of claim 12, wherein the firsttransistor and the second transistor are both P-type MOS transistors.14. The method of claim 13, wherein the switching speed of the firsttransistor is determined by the first voltage and the width-to-lengthratio of the first transistor, and the switching speed of the secondtransistor is determined by the second voltage and the width-to-lengthratio of the second transistor.
 15. The method of claim 11, wherein thestep of initiating application of a first column activation signal to afirst of the plurality of columns is performed in response to a logicsignal.
 16. A circuit for controlling the cells of a plasma screen ofarray type, formed of cells arranged at intersections of lines andcolumns, including line control blocks for sequentially activating eachline, and including column control blocks for, as each line isactivated, applying an activation potential to selected columns, eachcolumn control block including predetermined delay means for delayingthe application of the activation potential to the selected columns, thepredetermined delay means of each column control block being connectedto be activated by a same enable signal, the column control blocksforming a plurality of predetermined groups, the column control blocksof a same group applying said activation potential with a same delay andthe column control blocks of different groups applying said activationpotential with a different delay, said circuit also comprising means formodifying the value of each delay according to the number of selectedcolumns.
 17. The circuit of claim 16, wherein each column control blockincludes delay means comprising a NAND gate having a first input whichreceives a column selection signal, a second input which receives saidenable signal, and an output connected to the input of an invertersupplied between a ground and a supply node, the supply nodes of theinverters of a same group being interconnected, the supply nodes of theinverters of a first group being connected to a supply voltage and thesupply nodes of the inverters of each following group being separatedfrom the supply nodes of the inverters of a preceding group by aresistor.
 18. A process for controlling the cells of a plasma screen ofarray type, formed of cells arranged at intersections of lines andcolumns, including the steps of sequentially activating each line, and,as each line is activated, commanding by a same enable signal theactivation of the selected columns, wherein each selected column isactivated by a column control block with a delay particular to eachblock, the column control blocks forming a plurality of predeterminedgroups, the column control blocks of a same group activating the columnswith a same delay and the column control blocks of different groupsactivating the columns with a different delay, the value of each delaydepending on the number of selected columns.